? BCM1455 quad-core 64-bit mips ? processor (new!) ? four 64-bit mips ? cpus, scalable from 800 mhz?1.2 ghz quad-issue in-order pipeline with dual-execute and dual- memory pipes enhanced skew pipeline enables a zero load-to-use penalty 32-kb instruction cache and 32-kb data cache (ecc protected) fast on-chip multiprocessor bus connects the cpus, l2 cache, memory controller, and i/o bridges runs at half the cpu core frequency, and is 256 bits wide on-chip l2 cache 1 mb shared by four cpus and i/o agents eight-way associative, ecc protected any way can be programmed as fast on-chip ram ddr memory controller memory bandwidth as high as 100 gbps configurable as 2x64-bit or 4x32-bit wide channels runs up to 400-mhz clock rate, 800-mhz data rate support for ddr1, ddr2, and fcram integrated and network system i/o four gigabit-ethernet macs configurable as packet fifo interfaces 64-bit pci-x interface at 133 mhz generic i/o for direct connect to boot rom, flash memory two smbus serial configuration interfaces pcmcia control interface and up to 16 interrupts four uart interfaces on-chip debug capability ejtag bus trace unit (internal logic analyzer) support for leading operating systems, including vxworks ? , linux ? , qnx ? , and netbsd evaluation board platform available with samples (includes tools, firmware, and software drivers) industry-leading performance 2.5 dhrystone mips/mhz per cpu 20 million packets per second of l3 forwarding 128 gbps (@ 1.0 ghz) on-chip bus bandwidth, with 100 gbps memory bandwidth and over 31 gbps total i/o bandwidth low-power dissipation of 19w @ 1 ghz high functional integration, reducing overall system cost programming ease and flexibility based on mips64? instruction set architecture (isa) software compatible with bcm1250 and bcm112x broad tools and system software support features summary of benefits applications because of its world-class performance, power efficiency, and integration, the BCM1455 processor is ideal for a broad variety of applications, including: enterprise-class routers and switches multi-function security platforms (vpn/ssl/ids) high-end raid arrays san routers/gateways/switches wireless infrastructure plat forms (e.g. rnc, ggsn, msc) high-density computing bcm5690 12 x ge + higig BCM1455 4 x gmii (one/cpu) BCM1455 BCM1455 bcm5823 ddr dram bcm5823 ddr dram ddr dram bcm5823 pci high-density service card
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 1455-pb01-r 09/30/04 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain ot her countries. all other trademarks are the property of their respective owners. the BCM1455 device is an mips64 processor core-based system-on-a- chip (soc) that offers industry-l eading performance, high-functional integration, and low-power levels required by next-generation computing, storage, and networking applications. the BCM1455 is a chip multiprocessor (cmp ) system consisting of four broadcom sb-1 high-performance mips64 cpus, a shared 1-mb l2 cache, a ddr memory controller, and integrated i/o. all major blocks of the processor are connected together via the zbbus, which is a high- speed, split-transaction multiprocess or bus. the bus implements the standard mesi protocol to ensure coherency between the four cpus, l2 cache, i/o agents, and memory. four gigabit-ethernet macs (10/100/ 1000) enable easy interfacing to lans or control backplanes. to enable higher data rates (or in cases where ethernet protocol processing is not required), the gigabit-ethernet macs can be configured as 8-bit and/or 16-bit packet fifos. the BCM1455 also integrates a 64-bit, 133-mhz pci-x local bus for direct connection to i/o devices. four serial ports are available for use as uarts for console ports. to enable low-chip-count systems, the BCM1455 also includes a configurable generic bus that allows glueless connection of a boot rom or flash memory and simple i/o peripherals. on-chip debug, trace, and performance monitoring functions assist both hardware and software designers in debugging and tuning the system. the system can be run in either big-endian or little-endian mode. implementation of mips64 isa the sb-1 cpu core is a high-performance implementation of the standard mips64 isa that incorporates the mips-3d and mips-mdmx application-specific extensions (a ses). the core supports a 4-issue enhanced skew pipeline and can di spatch up to two memory and two alu (integer, floating point, mdmx, or mips-3d) instructions per cycle. 100 gbps 8 gbps 4x gmii 8b/16b fifo ddr memory controller zbbus tm 256 bits generic bus & flash i/o ? core clock; 128 gbps @ 1 ghz sb -1 core 64-bit pci - x dual smbus jtag sb -1 core gpio/ interrupt/ pcmcia data mover debug/ bus trace serial interfaces 10/100/ 1000 mac fifo dma 10/100/ 1000 mac dma 10/100/ 1000 mac dma 1 gbps 10/100/ 1000 mac dma i/o bridge sb -1 core sb -1 core sb -1 core sb -1 core 1 mb l2 cache next generation broadband processors bcm1255 bcm1280 BCM1455 bcm1480 # of cpus 22 44 l2 cache 512 kb 1 mb 1 mb 1 mb ddr2 support yes yes yes yes # of macs 4 gmii 4 gmii 4 gmii 4 gmii pci-x 1 x 64-bit 1 x 64-bit 1 x 64-bit 1 x 64-bit # of spi-4/ht ports 03 03
|
